NS9750 Microprocessor

The NS9750 uses an ARM926EJ-S core as its CPU, with MMU, DSP extensions, Jazelle Java accelerator, and 8 kB of instruction cache and 4 kB of data cache in a Harvard architecture. The NS9750 runs up to 200 MHz, with a 100 MHz system and memory bus and 50 MHz peripheral bus.

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Part Numbers

Supported

NS9750B-A1-C200NS9750B-A1-I162

Unsupported

NS9750B-0-C125NS9750B-0-C200NS9750B-0-I162NS9750B-A1-C125

Documentation

NS9750 Hardware Reference Manual

Drivers & Patches

OS Specific Patches

NS9750 Sample Driver Configurations

Resources & Utilities

NS9750 Boundary Scan Definition Language (BSDL)

NS9750B-A1 comparison to NS9750B-0

IBIS Information for NS9750

Hardware Resources

NS9750B-0 pinout listing

NS9750 Memory Reference Drawing

NS9750 PCI to Mini-PCI type III reference design

Hardware Installation Guide NS9750

LCD Displays Supported by the Digi NS9750/NS9360 Processors

NS9750 Power Sequencing

NS9750 schematic

NS9750 SDRAM Termination

NS9750 Memory SPICE Example

NS9750 PCI to Cardbus reference design

NS7520, NS9360, NS9750- Recommended Storage, Handling, Moisture Control and Reflow Conditions

Data Sheet

NS9750-0 Data Sheet

Solution Guides

NET+50 and NS7520 SDRAM Guide

NS9750 development board VERIBEST design file (sbk file)

NS9750 Jumpers and Components

Processor RoHS, marking, and availability chart (NET+40 through NS9750B-A1)

Application Note- NS9750, NS9775, and NS9360 Static Memory Access Limitation

IPC:JEDEC J-STD-020D1

Knowledge Base

The Digi AI Assistant combines product-specific knowledge articles, documentation, and the latest AI technology to formulate the most in-depth and current answers to your product questions.

NS9775, NS9750, NS7520 RoHS Compliance